SAN JOSE, USA
13 days ago
Principal Design Engineer
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Specific responsibilities:

Proficiency in logic design and micro-architectureProficiency in Verilog/SystemVerilog and its simulation environmentGood knowledge of IC design with high speed and low powerAt least six years experience working on digital IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.

     Position Requirements:

Essential Qualifications: Must have BS degree with 8+ years of applicable experience, MS degree with 6+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.Essential that the individual demonstrates strong communication, verbal and written.Requires good communication skills in English.Familiar with JEDEC-DDR, and DFI protocols and have memory IP design experience

The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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