At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Responsibilities

Design Verification for interconnect IPRelevant experience in interconnect and subsystems is strongly preferredCrafting verification plans and executing on those plans to verify highly complex and configurable designs.Responsible for coverage collection and closureWork closely with cross functional teams (DV/Arch/Design/FW) to identify coverage scope

Required Skills and Experience:

8+ years of design verification experienceBS (or higher) in EE/Computer EngineeringStrong technical and interpersonal skillsExcellent knowledge of Interconnects, NoCs and design verification fundamentals.Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenchesExperience with development of fully automated flowsExposure to scripting languages like Perl, Unix shell or similar languagesExperience with Formal Verification will be a plusExperience with Gate Level SimulationsExcellent written and oral communication skills necessary

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