At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Principal Engineer T4

Job responsibilities:

The engineer should have prior experience in most of the below responsibilities or keen to adapt 

Technical

Digital/DMS/AMS testbench creation and generationBehavioral Modeling in SV-RNM and Model Validation MethodologiesDefine AMS VPLAN for an IP to make sure all AMS features are covered in DVCreate Test strategy of replicating Silicon non linearities behavior on Analog signals such as jitter, noise effect, ISI  Mixed-Signal Assertions and CheckersPower intent verification including Low power states, state retention and CPF/UPF integrationPush technology for mixed-signal modeling, simulation and DV in order to improve mixed signal verification efficiency and accuracy.Ensure scalable mixed-signal DV solutions to cover the breadth of IPG offerings including SerDes, DDR, A2D converters and custom solutionsMentor junior engineers technically and collaborate closely with Digital, Analog, Firmware and Test engineers  , Internal methodology and tool development teams, such as, Virtuoso/ADE/Xcelium, PDK teams and Customer management and engineering support teamsAble to develop, run CO-SIMULATION for verification of Analog featuresLead and guide a team of 4-5 AMS engineerDocument the necessary methodology and test plan developed for better knowledge sharing among teams.We’re doing work that matters. Help us solve what others can’t.