At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

  Specific responsibilities will include:

Design and implementation of Tensilica software tool chain, in particular the instruction set simulator (ISS) for RISC-V processorsDevelopment of software models for RISC-V processor features for functional, cycle-accurate, and HW/SW simulation.Enhancements and maintenance of the existing RISC-V simulatorVerification of software models in hardware-software co-simulation environmentIntegration of the RISC-V instruction set simulator with 3rd party system modeling environments

 Requirements

MS or PhD in Computer Science or Electrical/Computer EngineeringBachelors in computer science or electrical Engineering + 7 years of related experience, or Masters + 5 years of related experience. Outstanding candidates with PhD and no industrial work experience will be considered.Strong C/C++ development skillsKnowledge of ISA, CPU micro architecture, and assemblyKnowledge of SystemC and TLM methodologiesExperience with GNU development tools and/or Microsoft Visual Studio environment Experience with modeling tools for performance analysis or Hardware/Software Co-simulationExperience in Electronic design automation (EDA) flowExperience developing software on Linux environmentAbility of reading specification and standard documents, and retrieving needed knowledge from various resources

The annual salary range for California is $131,600 to $244,400. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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