Job Description:
We are looking for Senior Engineer to join a growing, dynamic, and multi-cultural engineering team at the heart of a worldwide semiconductor CAD community. If your passion is to work in a challenging environment with a tremendous learning & growth potential, you can become one of us. Prospective candidate should be capable of understanding requirements and come up with creative solutions, following existing procedures but have a critical perspective regarding what they are doing and can tradeoff the optimal with the best on a daily basis.
Primary Responsibilities Include: Be part of a team that provides continued support on physical verification tools, flows and methodologies to our internal design R&D communities.Design, develop, troubleshoot or debug IC physical verification tools, runsets and flows used for the development of integrated circuits by global layout design team. Develop routines and utility programs to aid in verification of layout design.Build productive working relationships with cross functional teams.Key Qualifications:BS or MS degree in Electronic Engineering, Computer Science or similar.Proficiency with at least one programming languages like Python, Tcl, Perl.Exceptional desire to learn, explore new technologies and demonstrate good investigation and problem-solving skills.Familiarity with physical verification flows like LVS/DRC/FILL/DFM. Understanding of complex layout design rules and layout of complex semiconductor devices would be a plus.Prior knowledge and experience of tool/runset development/support is a plus.Experience with UNIX/Linux environment.Capability to produce adequate technical documentation.Has good communication skills and builds productive internal/external working relationships.