Sr. Staff R&D, RTL& Microarchitecture –
 
Our Silicon Lifecycle Management (SLM) business is all about building next-generation intelligent in-chip sensors, hardware/software capabilities and analytics to integrate into technology products to manage and improve each semiconductor lifecycle stage. We offer the world’s first full hardware IP, test, and end-to-end analytics to help customers integrate faster, optimize performance/power/area/schedule/yield, and enhance reliability. Meeting the unique challenges posed by various target applications, SLM enables differentiated products to market quickly with reduced risk.
 
Job Location : Bhubaneswar
Job Descriptions & Requirements
 
Part of the rapidly expanding Hardware-Analytics and Test (HAT) business unit, a RTL/Microarchitecture Sr. staff is chartered with leading the microarchitecture and RTL development of various SLM and PVT (Process, Voltage, Temperature) digital IPs as well as new upcoming IPs as part of HDG (Hardware Development Group) product portfolio. These would include but not limited to controller-subsystems, environmental sensors and performance monitors. The RTL/microarchitect Sr. staff will manage a team that designs new sensor & controllers as well as understand existing products and enhance them for better performance and automation friendliness. We are seeking an experienced, highly motivated, and high-caliber individual to build and lead this team. This individual should have strong technical experience in digital frontend design, backend implementation, timing, post-silicon characterization, PVT, DFx domains and possess excellent project execution and management skillsets. The candidate will actively help in recruiting a talented team to execute on these SLM projects and have leadership/management duties based on group’s requirement. Additional responsibilities include:Technical leader to drive Digital RTL for MSIP PVT Ips Understand business priorities and break it down into technical projects Understand existing products at lower levels and identify enhancement opportunities / cost Start as key architect and gradually build/ramp-up a team for these projects Look ahead into future opportunities and create a technical roadmap Establish processes, structures and methodologies for scaling and managing product execution Deployment of new digital IPs into test chips and post-silicon characterization  
Job RequirementsArchitectural and forward-looking thought process Sound knowledge of frontend digital design and verification BS or MS degree in Electrical Engineering with 4-10 years of relevant industry experience Experience managing complex projects and working with multiple stakeholders Experience hiring and managing medium sized teams, working with junior engineers Expertise both in RTL development and microarchitecture in IP or SOC level  Exposure to micro-architecture, design or verification of Digital hard IPs Demonstrated experience with multiple CAD flows: architecture and RTL design Experience with post silicon validation is a plus pointExcellent teamwork, communication, mentoring, and interpersonal skills with both internal teams and external customers  
 
Preferred skills:
 Strong RTL design , coding and microarchitecture development experience in Verilog, system Verilog, VHDL etc.Experience with writing structured RTL with architecture development ability Experience with coding state machines and Knowledge of one or more hard IPs and an exposure to SOC flowVerilog and System Verilog knowledge is a must.Demonstrated technical expertise in the productization of advanced technologiesExperience in PVT/Ring-Oscillator/DFx technologies and concepts is a strong plusStrong people management and leadership skills