Timing and PV Signoff Focus
Full flow place and route engineer with ~ 10 year experience.
TCL programmer
Signoff/Timing/DV experience
RTL to GDS exposure
Exposure to IP development.
Ideal candidate would have a broad scope of IP development from circuit design, DV, spice, extraction, PnR, signoff.
TCL programming experience with some flow development exposure.   Understanding use of namespace, procs, searching as well as various common algorithms.
In depth knowledge and hands-on experience of RTL to GDS implementation.
Ability to drive technical activities from detail specifications to release of product.
Ability to comprehend IP databook specifications.
PnR floor planning including block placement, power grid and clock routing impacts
General comprehension of RTL and Verilog design
The right candidate could grow into a technical project leader and/or technical product owner.
Previous AE or PE of SoC development could make a good candidate for this opportunity