Minimum qualifications: + Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. + 3 years of experience with Hardware IP design using Verilog/System Verilog and microarchitecture. + 3 years of experience with the Register-Transfer Level (RTL) quality check tool flows (e.g., Lint, CDC, RDC, Synthesis). Preferred qualifications: + Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. + 7 years of experience with the Register-Transfer Level (RTL) quality check tool flows (e.g., Lint, CDC, RDC, Synthesis). + 7 years of experience with Hardware IP design using Verilog/System Verilog and microarchitecture. + Experience with ARM-based SoCs, ARM-protocols, interconnects and ASIC methodology. + Experience with coding language like Perl or Python. + Experience with low power designs. Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be part of a team that designs interconnect IP for Pixel System on a Chip (SoCs). You will collaborate with members of architecture, software, verification, power, timing, synthesis etc. to specify and deliver quality Register-Transfer Level (RTL). You will solve technical problems with micro-architecture, RTL, low power design methodology and evaluate design options with performance, power and area. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. + Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc. + Perform Register-Transfer Level (RTL) development (e.g., SystemVerilog), debug functional/performance simulations. + Perform RTL quality checks including Lint, CDC, RDC, Synthesis, UPF checks. + Participate in synthesis, timing/power estimation. + Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCP_EEO_Post.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.