Senior Analog Chip Design Engineer
AirSwift
Senior Analog Chip Design Engineer
Summary
We are looking for a Analog Chip Design Engineer for a US Fabless Semiconductor MNC due to business expansion requirements.
The ideal fit will have experience in Schematic Capture, Optimization and Simulation of Analog circuits for risk identification, behavior prediction. You will lead the transistor designs to build efficient and reliable circuits to accomplish business objectives and long term design goals.
Job Responsibilities Schematic Capture, Optimization, and Simulation: Leading the Design and Optimization of analog circuits Lead the design and development of high-performance digital standard cell libraries, while ensuring that they meet design specifications. Working with Senior Engineers and Architects to find new logic families for the innovation of new digital standard cell architectures. You will be working closely with Layout Designers for layout and implementation of the circuits and cells. Reviewing of both design specifications and manufacturability meet the design-for-manufacturing (DFM) and design-for-test (DFT) practices and standards. Job Qualifications A Bachelor’s degree or higher in Electronics Engineering, Computer Science, or a related field is required. Advanced degrees such as a Master’s or Ph.D. are highly desirable. Relevant certifications in analog design or related fields will be considered a plus. 5 years of experience in high performance, low power Analog Designs on advanced manufacturing technologies (12nm, 7nm , 5nm) Familiarity with advanced analog-to-digital converters (ADCs) Good proficiency in Perl, TCL, Python and C++ programming language. Proficiency is schematic tools such as Candence Virtuoso, Innovus and Simulation tools. (Spectre, HSPICE) Hands on experience in development digital standard cell libraries. Able to communicate well with internal teams and be an independent team member will little supervision.
For further information or to arrange a confidential discussion, please apply with your updated CV to darren.ou@airswift.com. We regret to inform that only shortlisted candidates will be notified.
The ideal fit will have experience in Schematic Capture, Optimization and Simulation of Analog circuits for risk identification, behavior prediction. You will lead the transistor designs to build efficient and reliable circuits to accomplish business objectives and long term design goals.
Job Responsibilities Schematic Capture, Optimization, and Simulation: Leading the Design and Optimization of analog circuits Lead the design and development of high-performance digital standard cell libraries, while ensuring that they meet design specifications. Working with Senior Engineers and Architects to find new logic families for the innovation of new digital standard cell architectures. You will be working closely with Layout Designers for layout and implementation of the circuits and cells. Reviewing of both design specifications and manufacturability meet the design-for-manufacturing (DFM) and design-for-test (DFT) practices and standards. Job Qualifications A Bachelor’s degree or higher in Electronics Engineering, Computer Science, or a related field is required. Advanced degrees such as a Master’s or Ph.D. are highly desirable. Relevant certifications in analog design or related fields will be considered a plus. 5 years of experience in high performance, low power Analog Designs on advanced manufacturing technologies (12nm, 7nm , 5nm) Familiarity with advanced analog-to-digital converters (ADCs) Good proficiency in Perl, TCL, Python and C++ programming language. Proficiency is schematic tools such as Candence Virtuoso, Innovus and Simulation tools. (Spectre, HSPICE) Hands on experience in development digital standard cell libraries. Able to communicate well with internal teams and be an independent team member will little supervision.
For further information or to arrange a confidential discussion, please apply with your updated CV to darren.ou@airswift.com. We regret to inform that only shortlisted candidates will be notified.
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