Senior ASIC Design Engineer, Project Kuiper
Amazon.com
Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.
Key job responsibilities
- Gate Level Simulation: Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing. Analyze simulation results, identify and debug logic errors, and propose solutions. Work closely with design and verification engineers to validate fixes and ensure design closure.
- Facilitate seamless integration across Firmware, RTL, Platform Software, and Platform Drivers.
- Develop Debug tools: RTL Emulation, silicon bring-up, and functional validation.
Export Control Requirement:
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
A day in the life
Be part of Project Kuiper’s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies.
About the team
In this role you will:
· Work closely with the system architects to develop world-class SOC and IP blocks, which meet power, area and performance targets.
· Define, configure and integration SoC Subsystems
· Contribute to the SoC floor planning effort
· Define and develop any necessary support logic
· Configure, instantiate and integrate 3rd party IP blocks
· Understand low power design & the impact of DFT on the blocks
· Perform initial synthesis & timing analysis
· Assist verification team in unit verification including test plan development
· Assist with debug and bring-up
Key job responsibilities
- Gate Level Simulation: Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing. Analyze simulation results, identify and debug logic errors, and propose solutions. Work closely with design and verification engineers to validate fixes and ensure design closure.
- Facilitate seamless integration across Firmware, RTL, Platform Software, and Platform Drivers.
- Develop Debug tools: RTL Emulation, silicon bring-up, and functional validation.
Export Control Requirement:
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
A day in the life
Be part of Project Kuiper’s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies.
About the team
In this role you will:
· Work closely with the system architects to develop world-class SOC and IP blocks, which meet power, area and performance targets.
· Define, configure and integration SoC Subsystems
· Contribute to the SoC floor planning effort
· Define and develop any necessary support logic
· Configure, instantiate and integrate 3rd party IP blocks
· Understand low power design & the impact of DFT on the blocks
· Perform initial synthesis & timing analysis
· Assist verification team in unit verification including test plan development
· Assist with debug and bring-up
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