About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

This requirement is part of Central Engineering CAD organization. Central Engineering CAD , caters to flow and methodologies across various product BUs ,enhancing productivity, pushing PPA and enabling faster time to market.

What You Can Expect

Play a key role in supporting next-generation automated design flows and tools.Use extensive design and CAD expertise to guide flow and methodology support.Lead digital flow support across various Marvell Business Units.Address synthesis, P&R, STA, and power integrity flow issues.Contribute to the deployment and support of advanced design flows.Develop innovative solutions to evolving design challenges.Stay updated on process and tool advancements.Collaborate with EDA vendors and methodology experts for optimal tool and flow usage.

What We're Looking For

B.Tech/M.Tech in EE/CS with 10+ years of experience in physical design and flow development.Proven experience with 16nm or below nodes, preferably 7nm and 5nm.Familiarity with FinFET, Dual Patterning, and ULV challenges.Support RTL-GDSII flow and methodologies.Provide tools, flows, and methodologies for block and SoC levels for broader adoption.Create quality documentation for best-in-class flows and support the design community.Act as a liaison between the design and methodology teams to improve support and methodologies.Expertise in timing closure, synthesis, and constraint debugging.Knowledge of DFT is a plus but not mandatory.Experience with floorplanning, power grid design, and routability issues.Familiarity with clock synthesis schemes, SI, EM/IR, DRC, and power intent.Proficiency in implementing multiple power domains and addressing power integrity issues.Understanding high-speed and low-power trade-offs and upstream/downstream flow correlation.Knowledge of logical equivalence checks and CLP flows.Proficient in Tcl scripting for flow development and solutions.Working knowledge of SoC architecture, RTL, and pre-silicon functional verification is a plus.Strong problem-solving skills with innovative and proactive thinking.Effective team player with excellent communication skills.Advanced project management skills to deliver high-quality flows on time, ensuring first-time silicon success.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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