Role and Responsibilities

Help develop partitions and/or Integrate IPs into SoC Create partitions, and wrappers (RTL blocks) using Collage (TCL based integration tool flow) Use and/or define OSXML based register definition and run through OneSource tool to generate Design and Validation collaterals using Intel’s Cheetah based development flow Setup various design and verification flows such as: VCS compile, Lint run and cleanup, UPF, VCLP, CDC (ClockDomain Crossing) and RDC (Reset Domain Crossing). Either independently own and complete a partition from RTL development (collage-based design) to SD hand-off or assist a senior team member in existing team closely to enable them to achieve this.

 

Qualifications and Education Requirements

Bachelor’s or Master’s degree in electrical engineering Strong in digital concepts and Tools, Flow,methodologies 7+years of relevant experience in logic design, timing, analysis, Lint cleanup, andother ASIC design tool flow and methodologies. Self-motivated with ability to work with minimal supervision Experience with Intel’s Cheetah based flowand development methodology Team player with open mind Good communication skills to keep team lead in sync at all time both for good and not so good results

 

Preferred Skills

Collage, MGM, VCS H2B, R2G, UPF, VCLP SGLint, Jasper Gold SGCDC, VC_RDC PUNI, EFFM power Artist/PTPX

 

Benefits:

Private health subscription + hospitalization package; Private dental subscription; Gym subscription; Bookster; Vouchers/bonuses for special events (birthday, Christmas, Easter, etc); Meal vouchers of 35 RON/working day; Ability to work with a global company and immerse in a variety of international projects with different cultures within the IT industry; Access to cutting edge and state of the art technologies current with the everyday evolvement of technologies; Development opportunities with free access to over 3000+ training courses and peer-to-peer mentoring support.