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Lumentum Canada was awarded the 2022 National Capital Region’s Top Employers for the 6th consecutive year and the 2022 Career Directory Canada’s Best Employers for Recent Graduates for the 5th consecutive year.
 

Lumentum is seeking to hire a Senior FPGA Design/Verification engineer for our Ottawa based R&D team.
 

What do we do?

Lumentum (NASDAQ: LITE) is a market-leading manufacturer of innovative optical and photonic products enabling optical networking and commercial laser customers worldwide. Lumentum’s optical components and subsystems are part of virtually every type of telecom, enterprise, and data center network. Lumentum is headquartered in San Jose, California with R&D, manufacturing, and sales offices worldwide.  

We believe Lumentum is a great place to work, and we support a diverse and inclusive culture where employees bring their whole and authentic selves to work. Lumentum Ottawa has been recognized as one of National Capital Region's Top Employers.

What will you do?

The Opportunity...

This full-time position is an opportunity to work in a leading high technology telecommunications company. You will be part of a multidisciplinary team that develops a broad range of optical telecommunication products including next-generation optical switches and amplifiers.

In this role, you will work in both FPGA design and verification. In addition to working closely with the rest of the FPGA team, you will collaborate with other R&D engineering groups including hardware, firmware, algorithms, and verification.

In this role, you will be responsible for the following…
 

FPGA design: Architecture and implementation of control and datapath logic, IP core configuration and integration.Verification: Develop and maintain simulation environments, including scripts, testbenches, testcases, and bus functional models. Define and execute comprehensive verification plans.Lab validation & debugging: Collaborate with hardware and firmware engineers for cross-functional integration and lab validation, ensuring system-level performance goals are met. Develop and execute scripts for automated testing.Synthesis & optimization: Constraints implementation and optimization, thorough build and timing reports analysis to ensure robustness.Documentation: Create and maintain high-quality design and test documentation, contributing to project knowledge bases and future reference.Mentorship & Collaboration: Provide guidance to junior engineers and work with the team to foster best practices in design, verification, and methodologies. Welcome and provide feedback during design reviews.

Required Qualifications:
 

Strong experience in ASIC or FPGA design and simulation using Verilog/SystemVerilogStrong experience with synthesis, constraints, timing analysis, clock domain crossing.Team player working well with different functional groups and contributing effectively to multi-designer projects.Clear, robust and well commented coding style.Strong problem solving, troubleshooting and debugging skills.Excellent verbal and written communication skills.Thorough and detail oriented.

Assets:
 

Strong experience with AMD(Xilinx) or Altera FPGAs and tools.Experience with Constrained Random Verification, SystemVerilog Assertions, and advanced UVM methodologies.Experience with embedded processor SoC designExperience with PCIe, DDR memory, and AXI interfacesKnowledge of digital signal processing conceptsVHDL, C, Csh, Tcl, Python, PerlFamiliarity with Linux environment development