Job Description

Responsible for ensuring design robustness, testability and manufacturability of integrated circuits from the component feasibility stage through production ramp. Make significant contributions to design, development and validation of testability circuits. Contribute to evaluation, development and debug of complex test methods. Focus on product/IP DFx path finding as to ensure test methodology standardization and manufacturability robustness.

Responsibilities:
In this position, you will be responsible for server product test development. Your responsibilities will include but not be limited to:

Having close partnership with design and product development engineers to deliver Design-for-Test (DFT) solutionsDevelop DFX methodology which stick across product and methodology standardization which help to speed up post silicon debug processParticipating in DFT development like DFT architecture definition and test plans definitionResponsible for Verilog and/or VHDL test bench creation and/or debug, test writing, Register Transfer Level (RTL) simulation, Gate Level Simulation (GLS), analog simulation, performance validation, VTPSim (Verilog test pattern simulator), silicon debug on tester (or on other platform like system level)Developing highly optimized test vectors by using state-of-the-art vector conversion tool and methodsDeveloping, integrating and optimizing test program through characterization and other techniquesDeveloping or designing test hardware (for example test interface unit)Managing silicon debug to check out all the structural and functional testsQualifying new products and performing detailed test program analysis to ensure product startup with low Defect per Million (DPM), low test time, good yield and meeting other product health indicators before passing over to factory product engineering group for high volume manufacturing
Qualifications
Bachelor's degree in Electronics, Electrical, Microelectronics, Applied Mathematics, Statistics or Computer Engineering5 years above of experience in roles of circuit design engineering or PDE. Experience of full ownership and independent work on 3 full product cycle is a must.Knowledge in C++, Perl, VHDL, Verilog, digital logic, CMOS and hardware design is preferred.Knowledge of circuit design/Si process/test domains. SoC integrated circuit testing and high-volume manufacturing experience would be an added advantage.Strong analytical and problem-solving skills with a proven track record of creating and implementing integrated, multidiscipline solutions.Ability to work in unstructured environments and to initiate and drive new model path finding activity from ambiguity (concepts) to clarity (defined direction and development)Exceptional interpersonal communication, relationship management, effective listening and influencing skills that result in strong working partnerships across organization boundaries.
Inside this Business Group
The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.


Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.


Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.