About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Switch DFX team is responsible for overall DFT solution implemented in all Marvell Switch products. The team owns DFT Strategy, DFT Architecture, DFT IP's and all aspects of SoC MBIST and ATPG definition, implementation, validation pre and post-Si.

What You Can Expect

As a part of the DFT team the suitable candidate will work on all aspects of DFT in top notch Switch products: DFT architecture and Testability strategy, Flow, Implementation, Verification and post Si bring up.

You’ll work closely with other DFT team members for DFT features Implementation, Integration and Verification in SoC.

You will also have close interaction with Logic Design/Physical design/STA/ATE teams as needed.

What We're Looking For

Bachelor’s/Master's degree in Computer Science, Electrical Engineering or related fields with 7 to 10 years of related professional experience in DFT.

The candidate Marvell is looking for will have:

Very good knowledge on SCAN/ATPG/JTAG/MBIST

Proven experience on gate level simulations with no-timing and SDF based simulations for DFT modes

Proven experience on Test structures for DFT, IP Integration, ATPG Fault models, test point insertion, coverage improvement techniques

Proven experience in Scan insertion techniques at block level and Chip top level

Good knowledge on Test mode timing constraints

Cross domain knowledge to resolve DFT issues with design, synthesis, Physical design, STA team

Proficiency in Industry standard Tools for Scan insertion, ATPG, MBIST and JTAG. (Preferably Synopsys/Mentor tools)

Good Knowledge and understanding on JTAG for  IEEE1149.1/6 standards

Experience with Post-Si ramp up and debug on ATE

Good knowledge on Perl/ Tcl scripting skills.

Very good team player capabilities and excellent communication skills to work with a variety of teams across the global organization

High sense of responsibility and ownership within the team for successful Tapeout and Post -Si ramp up of the project

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

#LI-RS1