SOC Engineering, Principal Engineer
CoWare
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
CAD Methodology, Principal Engineer
Responsibilities:Process, Voltage and Temperature recommendation and corner selection for a given project.Setup a methodology for Timing Signoff that includes POCV settings, Margining methodology (jitter/setup/hold margins), correlation between Implementation and signoff toolsNew Technologies enablement for design services that include path finding for new node, Radiation Hardening(A&G programs) , Autograde signoff criteria etcTiming constraints methodology and template ownership for generating timing constraints for all modesLow Power methodology, UPF template ownership , ramp-up/ramp-down IR drop analysisHPC – Create and manage methodologies for custom power grid , High speed custom clock trees , Decap , EMIR , ESD , Spice analysis of clock treesSupport ongoing projects with Performance/Power/Area improvements.Tapeout related foundry interface involving PDK/mock-tapeouts/e-job views etcRequired Skills:Excellent understanding of the ASIC development cycle and full-chip SOC flows.Familiar with all the Synopsys EDA tools used for RTL2GDS flows.Very sound in developing algorithms and scripts for high speed/performance and low power design methodologies and flows.Familiar with new chip design technologies involving chiplets,D2D interafces,3DIC etcExceptional in programming languages(C/C++/Python/Perl/TCL etc) to help with AutomationExtensive experience in partnering across functional teams.Experience working in a customer centric environment.Qualifications:Minimum 12 years of industry experience.Bachelor’s or Master’s degree in electrical engineering
The base salary range across the U.S. for this role is between $159,000-$239,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
CAD Methodology, Principal Engineer
Responsibilities:Process, Voltage and Temperature recommendation and corner selection for a given project.Setup a methodology for Timing Signoff that includes POCV settings, Margining methodology (jitter/setup/hold margins), correlation between Implementation and signoff toolsNew Technologies enablement for design services that include path finding for new node, Radiation Hardening(A&G programs) , Autograde signoff criteria etcTiming constraints methodology and template ownership for generating timing constraints for all modesLow Power methodology, UPF template ownership , ramp-up/ramp-down IR drop analysisHPC – Create and manage methodologies for custom power grid , High speed custom clock trees , Decap , EMIR , ESD , Spice analysis of clock treesSupport ongoing projects with Performance/Power/Area improvements.Tapeout related foundry interface involving PDK/mock-tapeouts/e-job views etcRequired Skills:Excellent understanding of the ASIC development cycle and full-chip SOC flows.Familiar with all the Synopsys EDA tools used for RTL2GDS flows.Very sound in developing algorithms and scripts for high speed/performance and low power design methodologies and flows.Familiar with new chip design technologies involving chiplets,D2D interafces,3DIC etcExceptional in programming languages(C/C++/Python/Perl/TCL etc) to help with AutomationExtensive experience in partnering across functional teams.Experience working in a customer centric environment.Qualifications:Minimum 12 years of industry experience.Bachelor’s or Master’s degree in electrical engineering
The base salary range across the U.S. for this role is between $159,000-$239,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
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