DutiesUnderstand Complete ASIC Design Verification Flow and Customize according to end Application.Build a Complete Verification flow using an existing design from RTL to GDS.Modify Methodology/Constraints to accommodate our Recommended Verification FlowDefine data trends and build checkers to validate the flow.Automate Complete Solution, with self-monitoring trend analytics and Regression trends.Required QualificationsBS or MS degree in Computer Science, Electrical or Computer Engineering, or Related Field with 7+ years of experienceKnowledge of Digital design verification(Dynamic/Static),  Verilog/VHDL and associated verification tools.Experience in Complete Verification Methodology and understand what’s needed from verification perspective to Signoff a design.Proven HDL experience in SystemVerilog/HDL/SVA and UVM methodologySoftware experience with Python/C++/TCL scripting knowledge