Company:Qualcomm Semiconductor Limited

Job Area:Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Responsible for next-generation workflow automation for TECH IP engineers.

Design, develop, deploy, and improve highly scalable, long shelf-life workflows and automation platforms for compute and memory-heavy workloads.

Deconstruct user workflows into actionable tasks and plan a pathway to automation.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.

Master’s degree in Electrical Engineering, Computer Science, or a related technical field.

With 3+ years of experience in software development, and with data structures/algorithms.

With 3+ years of python coding experience.

Excellent grasp of workflows and UNIX processes, concurrency and load-balancing.

Understand LSF infrastructure is a plus.

Experience in the semiconductor industry is a plus.

Experience in developing machine learning algorithms is a plus.

Self-driven, detail-oriented, strong teamwork and collaboration skills.

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