Build your career with Jabil! We challenge and empower you to make most of your talents, working with outstanding colleagues from diverse backgrounds who share your drive and passion to make Jabil grow!
JOB SUMMARY
Under the guidance of management, develops new engineering design of a basic to moderate complexity. Gathers design requirements and recommends steps to implement basic to moderate reference design. implementation or design modifications of existing product. Perform and analyze basic to moderate circuit design, referring more complex issues to management or more senior team members. Develop subsystem architecture at the direction of a Sr. Engineer or above.
ESSENTIAL DUTIES AND RESPONSIBILITIES
Work closely with Hardware, BIOS, BMC, and Firmware team for CPLD / FPGA design, validation, and maintenanceDevelop Server / Storage production power on sequence control logic by CPLD / FPGAImplement new technology and design concept in CPLD / FPGADesign test plan, development specification, and issue trackingJOB QUALIFICATIONS
KNOWLEDGE REQUIREMENTS
TECHNICAL KNOWLEDGE & SKILLS
1~5 years of working experience in CPLD / FPGA developmentFamiliar with CPLD / FPGA design and Verilog/VHDL codingExperience in I2C, SPI, UART, and SGPIO protocolsExperience in RTL coding and simulation is a plusBuilding in the area of CPLDs and FPGAs including coding practice, RTL coding standards, using Git, building test benches, etc.Familiar with C language, PFR, and eclipse.NON-TECHNICAL KNOWLEDGE & SKILLS
Influence others and share best practices.Effectively communicate with good understanding of English.Work as part of a global team.EDUCATION & EXPERIENCE REQUIREMENTS
Electrical Engineering Degree (BSEE/MSEE or equivalent experience)1+ years experience in CPLD / FPGA design or other key competencyOr an equivalent combination of education, training or experience.Domestic and international travel is required (within 1 month)
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