Position Responsibilities:

Designing and implementing video compression logic, image processing logic, vector processing and neural network accelerator logics, processor cores, and memory sub-system in Verilog and System Verilog. Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages. Synthesize and optimize RTL for timing, area and power. Developing front-end methodologies and tool flows. Participating in chip bring-up and testing. Analyzing and reviewing code coverage and functional coverage, and providing recommendations to the verification team to address any gaps.

 Requirements:

Master’s degree in Electrical/Electronics/Computer Engineering with 0-5 years of experience. Good understanding of computer architecture, logic design and VLSI design. Knowledge of System Verilog, Verilog, and Perl. Knowledge of design verification, and functional coverage. Ability to program scripting languages and the ability to write assembly language programs. Strong communication skills and a good team player. Adept problem solving abilities Knowledge of logic synthesis and timing closer is a plus

The base salary range is $135,000 - $170,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We also offer new hire RSU grants and the opportunity for annual RSU grants, as well as other highly competitive benefits.