Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.

The Role:
Be part of Project Kuiper’s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies.

In this role you will:
• As the implementation lead you will set up the flow for both logic and physical synthesis flow for various technology nodes.
• Work with the ASIC design and DFT teams to understand the design and create timing constraints.
• Check the RTL design for clean synthesis run, perform STA and LEC on netlist.
• Work with RFIC teams to make sure the top level integration of analog blocks are done properly and correct by construction, including formal connectivity checks.
• Work with P&R teams to ensure a smooth hand off of netlists, ensure the timely execution of the P&R responsibilities by that team.
• Participate in flow reviews of all the blocks with the P&R team to ensure that they achieve the best PPA for all blocks.
• Lead the timing sign-off for the post P&R database.
• Ensure that the chip meets the required DFM criteria by verifying the IR/EM results.


Export Control Requirement:
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.