Our Exciting Opportunity:
Physical Design DFX Engineer
The Ericsson Radio and Baseband Products have our ASICs as their backbone, and our challenge is to design and deliver those so that our 5G leadership position in the market accelerates. Our ASICS will be challenging when considering the overall combination of size/complexity, power, performance targets, advanced process node technology, and pushing the design methodology on an ongoing basis. We are looking for a Senior DFX Engineer to join us and be a part of this just starting DFX team. The role will help build the initial DFX team, define strategy for long term, including all aspects of DFX (Architecture, Design Methodology, Test, Silicon Debug). It includes working closely with other functions within Austin and in Sweden as the design takes shape at the IP, SOC, and system level to ensure that the final ASIC achieves the program goals. You will also work closely with our partners and other sites as we continue to build out our capability as we compete with the best in the world to maintain our leadership position.
You will:
Contribute to building of a world-class, brand new DFX team
Strategize, architect, plan, design & implement full DFT capability from scratch
Partner with Test Team to define overall test strategy
Partner with Physical Design teams (IP & SOC) to develop complex SOCs
Work closely with EDA Vendors & CAD team to define next generation DFT flows and methodology with latest & greatest features
Mentor & coach junior engineers within the team and helping them achieve their goals
Collaborate with cross site / geography teams to help establish great working relationship and deal very efficiently with deliverables across teams
To be successful in the role you must have:
12+ years of experience (10+ years with MSEE) working at a senior level role in SOC/IP/ASIC design team with an emphasis around DFX (DFT/DFD/DFM)
Minimum Education: BSEE
Must have expert level, working knowledge about DFX standards and practices, ATPG, Scan, JTAG, iJTAG, BIST, including trade-offs between test quality, test time, efficiency and their impact to overall design implementation
Experience with SOC level DFT planning, architecture, and execution.
Understanding of industry road map on DFX and active contributions towards improvements in DFX working with industry experts
Good focus on automation & infrastructure to enable efficient execution pipeline within DFX function
Experience with post silicon debug, yield bring up, test-time and pattern delivery while working closely with TEPE teams for long term strategic improvements
Continuous drive to improve flows, methodology and architecture for enabling scalability of the overall team in years to come
Understanding of Physical design implementation flows and methods to enable a smooth integration of DFT in the design with efficient and quality hand offs
What´s in it for you?
Here at Ericsson, our culture is built on over a century of courageous decisions. With us, you will no longer be dreaming of what the future holds – you will be redefining it. You won't develop for the status quo but will build what replaces it. Joining us is a way to move your career in any direction you want; with hundreds of career opportunities in locations all over the world, in a place where co-creation and collaboration are embedded into the walls. You will find yourself in a speak-up environment where empathy and humanness serve as cornerstones for how we work, and where work-life balance is a priority. Welcome to an inclusive, global company where your opportunity to make an impact is endless.
What happens once you apply?
To prepare yourself for next steps, please explore here: https://www.ericsson.com/en/careers/job-opportunities/hiring-process
Hiring Manager--Anurag Jindall
Recruiter--James Robinson
External Description
External Description
Our Exciting Opportunity:
Physical Design DFX Engineer
The Ericsson Radio and Baseband Products have our ASICs as their backbone, and our challenge is to design and deliver those so that our 5G leadership position in the market accelerates. Our ASICS will be challenging when considering the overall combination of size/complexity, power, performance targets, advanced process node technology, and pushing the design methodology on an ongoing basis. We are looking for a Senior DFX Engineer to join us and be a part of this just starting DFX team. The role will help build the initial DFX team, define strategy for long term, including all aspects of DFX (Architecture, Design Methodology, Test, Silicon Debug). It includes working closely with other functions within Austin and in Sweden as the design takes shape at the IP, SOC, and system level to ensure that the final ASIC achieves the program goals. You will also work closely with our partners and other sites as we continue to build out our capability as we compete with the best in the world to maintain our leadership position.
You will:
Contribute to building of a world-class, brand new DFX team
Strategize, architect, plan, design & implement full DFT capability from scratch
Partner with Test Team to define overall test strategy
Partner with Physical Design teams (IP & SOC) to develop complex SOCs
Work closely with EDA Vendors & CAD team to define next generation DFT flows and methodology with latest & greatest features
Mentor & coach junior engineers within the team and helping them achieve their goals
Collaborate with cross site / geography teams to help establish great working relationship and deal very efficiently with deliverables across teams
To be successful in the role you must have:
12+ years of experience (10+ years with MSEE) working at a senior level role in SOC/IP/ASIC design team with an emphasis around DFX (DFT/DFD/DFM)
Minimum Education: BSEE
Must have expert level, working knowledge about DFX standards and practices, ATPG, Scan, JTAG, iJTAG, BIST, including trade-offs between test quality, test time, efficiency and their impact to overall design implementation
Experience with SOC level DFT planning, architecture, and execution.
Understanding of industry road map on DFX and active contributions towards improvements in DFX working with industry experts
Good focus on automation & infrastructure to enable efficient execution pipeline within DFX function
Experience with post silicon debug, yield bring up, test-time and pattern delivery while working closely with TEPE teams for long term strategic improvements
Continuous drive to improve flows, methodology and architecture for enabling scalability of the overall team in years to come
Understanding of Physical design implementation flows and methods to enable a smooth integration of DFT in the design with efficient and quality hand offs
What´s in it for you?
Here at Ericsson, our culture is built on over a century of courageous decisions. With us, you will no longer be dreaming of what the future holds – you will be redefining it. You won’t develop for the status quo but will build what replaces it. Joining us is a way to move your career in any direction you want; with hundreds of career opportunities in locations all over the world, in a place where co-creation and collaboration are embedded into the walls. You will find yourself in a speak-up environment where empathy and humanness serve as cornerstones for how we work, and where work-life balance is a priority. Welcome to an inclusive, global company where your opportunity to make an impact is endless.
What happens once you apply?
To prepare yourself for next steps, please explore here: https://www.ericsson.com/en/careers/job-opportunities/hiring-process