Company:Qualcomm Atheros, Inc.

Job Area:Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a Design Verification Lead, you will lead a team of ASIC design verification engineers to verify IP and Subsystems that be integrated in a variety of Qualcomm WIFI, connectivity and IOT devices. You will work closely with SoC Architects, software, validation and design teams to verify IP that meets power, performance and area goals for Qualcomm Wireless and connectivity products. You will lead a team defining the processes, methods and tools for design verification of large complex IP blocks and subsystems.

Job Responsibilities

Lead Sub-System & SoC Design verification for Qualcomm WIFI projectsOwn end-end low power test bench architecture, test plan and coverage driven verification closureCollaborate with  cross geo teams for various IP, SOC and VI deliveries, milestone planning & critical debugsBuild, manage and mentor a team of ASIC DV engineersExplore innovative DV methodologies (formal, simulation, and emulation strategies) to continuously push the quality and efficiency of test benchesAct as a technical point of contact to the different IP and SoC design teamsProvide technical leadership through personal example, mentorship, and strong teamwork

Required Skillset

Experience with various aspects of digital verification such as test automation, code and functional coverage, constraint randomization, system Verilog assertions, and performance.Strong System Verilog / UVM based verification skills, experience with assertions, and coverage-based verification methodologyStrong leadership,  Analytical and problem-solving skillsExperience with C/C++, assembly language.Knowledge of low power design concepts and power management is a big plus.Strong team player and communicatorExperience with AMBA bus protocolsExperience with GLS, and scripting languages such as Perl, Python is a plus8+ years or more of practical semiconductor ASIC DV experience including owning end-to-end verification of major SoC blocks2+ years’  leadership experience taking  projects to Tape out

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

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Pay range and Other Compensation & Benefits:

$176,300.00 - $264,500.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm.  We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).  In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.