Company:Qualcomm India Private Limited

Job Area:Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Job Description

Responsibilities:

Experience : 5 to 10 yearsSTA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.Evaluate multiple timing methodologies/tools on different designs and technology nodes.Work on automation scripts within STA/PD tools for methodology development.Good Technical writing and Communication skills, should be willing to work in cross-collaborative environmentExperience in design automation using TCL/Perl/Python.Familiar with digital flow design implementation RTL to GDS : ICC, Innovus , PT/TempusFamiliar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Education : B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI.

Preferred Qualification/Skills

Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handlingHands-on experience with STA tools - Prime-time, TempusHave experience in driving timing convergence at Chip-level and Hard-Macro levelIn-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.Proficient is scripting languages – TCL, Perl, AwkBasic knowledge of device physics

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