Company:Qualcomm India Private Limited

Job Area:Engineering Group, Engineering Group > Hardware Engineering

General Summary:

General Summary:

ResponsibilitiesStrong design understanding with focus on all timing closure aspectsDevelop timing constraints and provide constraints support for PD STA and interface timing closure.Review timing with cross functional teams, provide feedback and sign-off.Critical path review and on-die uncertainty evaluations.Provide support to SoC integration and chip level pre/post-silicon debug.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Skills & ExperienceMTech/BTech in EE/CS with hardware engineering experience of 2-6 years.Experience in timing closure and debug of complex IPStrong exposure to PT/Tempus flows, scripting (TCL, Perl/Python)Able to work with teams across the globe and possess good communication skills.

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