About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

CE AMS FIP Analog Layout: Central Engineering develops SoCs for various end markets in advanced process technologies and analog mixed-signal and advanced packaging development, including foundational IP and system hardware. CE AMS IP function develops foundational technology for Marvell’s multiple analog product lines.

This role is crucial in the semiconductor industry, ensuring that high-performance analog circuits are accurately and efficiently implemented on silicon. Advanced nodes push the boundaries of what’s possible in analog design, requiring innovative layout approaches and tools to manage the increased complexity and variability.

What You Can Expect

Perform physical layout for mixed-signal design like high speed ADC, PLL's, Bandgap Voltage Reference, LDO, high speed I/O circuits, general I/O's, ESD structures designs in deep sub-micron CMOS technologies.

Closely work with circuit designer across different geographies.

Responsible for floor planning, custom layout design and run physical verifications and sign off for the release.

Mentoring junior layout engineers.

As a key member of Marvell's Central Engineering team, you will play a leading role on developing next-generation high speed SerDes IPs.

We work with leading edge finfet technologies to produce best-in- class analog IPs which enable us to move, store, process and secure the world's data faster and more reliable​

What We're Looking For

Marvell is seeking a Layout engineer to contribute to the development of High-Speed SerDes, ADC, PLL's, LDO, I/O circuits, general I/O's, ESD structures.

Bachelor’s or master’s Degree and or PhD in Electrical/Electronics Engineering, Microelectronics or related fields with 4 to 8 years of related professional experience.

Good understanding of advanced semiconductor technology process and device physics.

Full-custom circuit layout/verification and RC extraction experience. Experiences in one or more of the following areas is preferable : Mixed signal/analog/high speed layout, e.g. SerDes, ADC/DAC, PLL, etc.

Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM, etc).

Experience in advanced technology nodes like 2nm/3nm/5nm is preferable.

Experience with EMIR analysis, ESD, antenna and related layout solutions.

Good communication skills and willingness to work with global team.

Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.

Programming skills, automation and circuit Design background is a plus.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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