8-10 Years Tape out experience in block level and full chip floorplanfull chip partitioning flow.
Experience in independently analyzingresolving congestion, timing issues and basic understanding of clock tree build
Timing understanding to independently analyze timing paths
Experience in 16/14nm or below flows.
Experience in die-size estimation spread sheet IP based and synthesis based
Experience in IO/Bump planning placement, custom analog/PG planning and route implementation
Equivalence check understanding. Good to have Conformal LEC experience
Experience in ICC2/Innovus/DC tools
Experience in RDL routing
Experience in interfacing with cross functional teams and block PnR teams
Good understanding of basic shell scripting, tool based TCL scripting to automate all custom activities
Experience in version control systems
Experience in managing/mentoring small teams
(1.) To architect, design and develop [through team] solution for product or sustenance delivery. (2.) To train and develop team so as to ensure that there is an adequate supply of trained manpower in the said technology and delivery risks are mitigated. (3.) To ensure knowledge up-gradation and work with new technologies so that the solution is current and meets quality standards and the client requirements. (4.) To gather specifications and deliver solutions to the client organization based on understanding of a domain or technology.