Role Description:
The VLSI Physical Design Engineer is responsible for implementing and optimizing the layout of integrated circuits (ICs) from netlist to GDSII. This role plays a key part in turning high-level logic designs into manufacturable silicon chips, ensuring electrical performance, area, and power (PPA) goals are met, and the physical verification results are good.

Key responsibilities:
1. Derive full-chip and block-level physical design from netlist to tape-out (netilst to GDSII).
2. Floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and layout verifications.
3. Work closely with front-end design, DFT, and package teams to ensure design closure.
4. Sign-off on signal integrity, power integrity, reliability and manufacturability including performing static timing analysis (STA), IR drop analysis, EM analysis, and physical verification (DRC/LVS/DFM).
5. Analyze, optimize and resolve congestion, timing, power integrity and signal integrity issues.
6. Create and maintain physical design automation Tcl scripts, and flows development for design implementation.
7. Interface with EDA tool vendors and foundries to ensure design compliance and manufacturability.

Requirements: 
1. Minimum Master degree majoring in EE/CE/CS related fields.
2. At least 2 years and 7 years of experiences in VLSI field for designer and manager positions, respectively.
3. Experience in tapeout with multi-million gates count SOC design, 10/7/5/3nm design experience is a plus.
4. Solid skill sets of one of Cadence/Synopsys/Mentor EDA tools.
5. Experience in design methodology, flow deployment/refinement and problem solving skill.
6. Familiar with Perl/TCL scripting is a plus
7. Proficiency in speaking and writing English is a plus.
8. Good communication skill, team spirit, initiative, innovative and fast learning.