Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc.
People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.
Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.
Visit our careers page to see what exciting opportunities and company perks await!
Job Description:
Microchip’s Data Center Solutions (DCS) Business Unit offers industry leading performance, reliability, and security for PCIe Switches, and NVME Controllers. As a Principal Engineer-Design, you will provide leadership in the highly successful PCIe Switch product line. These complex 800M gate+ integrated silicon devices enable top tier data centers in next gen storage, artificial intelligence and automotive market segments.
As a Principal Engineer-Design , your job will entail the following:
Requirements/Qualifications:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or equivalent8+ years related experienceRTL Design - Experience in RTL Design using System Verilog, Verilog is required. Experience and understanding of complex ASIC design flows, including block and chip level simulation and debug, logic synthesis, static timing analysis, layout and revision controlExperience with Formal Verification a plus.Working knowledge of design and verification tools such as Synopsys Design Compiler, Cadence Incisive, waveform viewers, and other similar tools.Scripting and programming skills using csh, bash, perl, python, tcl, etc. Protocol knowledge and experience in PCI-Express will be an assetKnowledge of AHB/AXI bus protocols is desired.Excellent knowledge in logic synthesis and static timing analysis.Experience in designing the chip top level with IOs, pin out and package designWorked with physical design teams for layout implementation. Familiar with low power methodology and flows.Capable of debugging EDA tool issues or design related issues.Working knowledge of DFT. Excellent analytical and debugging skills and the ability to proactively solve issuesGood verbal and written communication skills in English will be an assetExcellent teamwork and time management skills, self-direction, the ability to work under pressure and the desire to excel in a ompetitive environmentTravel Time:
0% - 25%Physical Attributes:
Hearing, Other, Seeing, Talking, Works Alone, Works Around OthersPhysical Requirements:
100% inside, 80% sitting, 10% walking, 10% standingMicrochip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.
For more information on applicable equal employment regulations, please refer to the EEO is the Law Poster and the EEO is the Law Poster Supplement. Please also refer to the Pay Transparency Policy Statement.